Process development needs hierarchy, abstraction, says tools CTO
Semiconductor process development lacks tools that offer the same kind of support for hierarchy and abstraction that have enabled chip designers to handle the vast increase in capacity of modern processes, according to David Fried, CTO of Coventor, which provides the Semulator 3D software used to produce our finFET tipsheet.
Speaking at a reception at IEDM in San Francisco this week, Fried argued that there is a mismatch between the cost of building a fab and establishing a new process in it and the sophistication of the tools used to help develop the processes.
“To put a new technology into a fab costs $2bn or more and all that money gets spent before you run a single revenue-generating wafer,” he said. Fried estimates that a single technology trial to test a process development could cost up to $50m, on the basis of doing 40 wafer starts a day and running 150 5-way experiments, all subject to variation and with the variable you’re trying to test potentially being affected by unwanted process changes, and all needing characterisation and analysis.
Fried argued that EDA tool vendors had been able to ensure that designers could cope with the vast increase in the capacity of IC processes by building a hierarchy of fast tools that offer increasing levels of abstraction and which check a designer’s work as they go along.
“On the [process] technology side we don’t have that organised hierarchy,” he said. “We have process models and TCAD but these are slow and low level and offer limited checking.”
Unsurprisingly, Fried presents the SEMulator 3D tool as “the next level of hierarchy”, built for “speed at the right level” and incorporating physical checking as you go along.
Does it work? IBM, where Fried was until August lead technologist for the 22nm process that was unveiled at the conference on Monday, used SEMulator 3D to explore various process issues such as variations in the way that source and drain contacts were produced.
Fried’s argument is that the predictive model of a process that underlies the operation of SEMulator 3D enables functions such as virtual measurements, batch modelling for variability analysis, and parallelism for computing speed. “Computational technology development” means that the multiple, expensive process experiments that Fried described earlier can be done in the computer not the fab, saving time and money and offering other advantages, such as the ability to ensure that only the parameters that you want to vary are allowed to change.
The tool can also be used to explore issues such as layout variation, taking users into the realm of technology development. Adding adaptive analysis, so that users can explore ‘what if’ questions, leads to opportunities to co-optimise the process technology and design aspects of a new manufacturing offering.
“We’re not trying to replace TCAD,” said Fried, “we’re trying to solve problems at the right level with the right tool, working at a higher level of abstraction where we can model phenomenological behaviour.”
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