The specialist AMS foundry Triad Semiconductor has married its ViaASIC drag and drop libraries to Mentor Graphics' SystemVision design environment.
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.
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