Design to Silicon

April 2, 2012

Mixed-signal for the rest of us from Triad

The specialist AMS foundry Triad Semiconductor has married its ViaASIC drag and drop libraries to Mentor Graphics' SystemVision design environment.
March 26, 2012

Synopsys builds 3D into tool portfolio

At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
March 22, 2012

TSMC Altera heterogeneous integration is cool but is it 3D?

This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
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March 20, 2012

Japan one year on: a need to rebuild exposed?

Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
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March 16, 2012

DATE 2012: Coverage roundup

This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.
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March 16, 2012

DATE notebook: Aldec builds in more support for VHDL methodology

Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
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March 16, 2012

DATE notebook: Help for heat-sensitive chips

Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.
March 15, 2012

DATE notebook: Constraints smooth path for FPGA synthesis

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
March 15, 2012

CPTF notebook: From restricted to ‘proscriptive’ design rules

Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
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March 15, 2012

CDN Live: Cadence’s Encounter revamp collates innovation

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.

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