Can process migration tools help the yield-challenged and speed the path to 20nm?
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
Cutting the cabling to simplify the emulation process.
Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
SpringSoft is trying a different approach to constraint-based design in a bid to improve the automation of custom and mixed-signal design, particularly on advanced process nodes.
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