Design to Silicon

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.

You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.

FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.

Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.

Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors