Design to Silicon

September 6, 2012

Getting ready for 20nm

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
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August 6, 2012

TSMC joins Intel as ASML investor to accelerate availability of EUV, 450mm lithography

TSMC follows Intel in taking a stake in ASML to accelerate development of EUV and 450mm lithography equipment.
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August 6, 2012

Aart de Geus on the changing face of EDA

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
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June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
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June 12, 2012

Doping gives finFETs threshold control

You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.
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June 11, 2012

Degrees of freedom for finFETs

FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.
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June 11, 2012

FD-SOI to get foundry push in ST deal

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.
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June 6, 2012

DAC 2012: Intel’s Ivy Bridge chip chop shop

Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
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June 5, 2012

DAC2012: Collaboration key to success at 20nm

Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors
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June 5, 2012

DAC 2012: ARM tips subthreshold power-gating technique

Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
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