IEF: Process kits for processes that don’t yet exist

By Chris Edwards |  No Comments  |  Posted: October 5, 2012
Topics/Categories: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,  | Organizations:

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, Rudy Lauwereins, vice president of the smart systems technology office at research institute IMEC, told delegates at the International Electronics Forum (IEF) in Bratislava this week.

“To develop 10nm or 7nm technology there are so many options that we have to look at design to decide which options to take,” said Lauwereins. “Setting the technology targets is starting more and more from design. It’s all about finding the right sweet spot.”

IMEC’s plan revolves around the use of pathfinding process design kits (PDKs) to evaluate how designs will be affected by the properties of future technologies – in each case resynthesizing candidate designs to make best use of each.

“The way we reach performance targets will be different for each technology. We have to know what the impact of the various options will be.”

By looking at the needs of design rather than focusing primarily on traditional figures of merit such as drive current and leakage, the IMEC Insite work resembles some of the technology pathfinding performed in previous years by the joint NXP/TSMC research labs, which showed several years ago that finFETs were beginning to show better properties for mobile products than conventional bulk CMOS processes.

The problem facing process designers now is the expanding range of options now on the horizon as it becomes clear that silicon, even with the massive amounts of strain imposed on the transistor channel to improve mobility, is running out of steam. III-V devices may appear in time for the 10nm process but may not necessarily be based on conventional switching schemes. Heterojunction devices based on III-V devices make the tunnel FET feasible, which could offer much better power consumption. However, unless their leakage and current drive properties improve, junction-less nanowire devices may instead become the norm.

“We keep as many options open as possible. With the TFET, we are quite convinced we can get leakage [under control] but we are not convinced that we can get that done at the right current drive. So we are working on junction-less transistors at the same time,” Lauwereins said.

“Things are introduced much later than when people think. I’m not sure III-V will be introduced with 10nm. This is why pathfinding PDKs are so important: they help to keep options open. So we can see that if TFET doesn’t make it we can see what junction-less will give instead. You keep all your options open and then understand what the impact of each will be,” Lauwereins said.

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