Siemens EDA

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.

ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.

Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.

Read some edited highlights from the most successful companies in Mentor's 2017 Technology Leadership Awards.

A new version of automotive safety standard ISO 26262 is due in 2018 but how close to Level 5 autonomy will it actually take us? And what about security?

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.