PCI Express


May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
February 13, 2018

HyperLynx update automates SerDes validation

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Article  |  Topics: Blog Topics, Blog - PCB, - Product  |  Tags: , , , , , ,   |  Organizations:
May 18, 2015

Vehicle ethernet adds to IP virtual reference kits for board design

Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , ,   |  Organizations:
June 2, 2014

Synopsys uses virtual prototyping kits to kick start IP integration

Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations:
March 5, 2014

Visual timing tool focuses on high-speed PCB signals

Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
December 4, 2012

IPSoC: Tabula aims for 22nm white-label parts

Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , ,   |  Organizations: ,

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