PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
PCI Express
HyperLynx update automates SerDes validation
Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Vehicle ethernet adds to IP virtual reference kits for board design
Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.
Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Visual timing tool focuses on high-speed PCB signals
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
IPSoC: Tabula aims for 22nm white-label parts
Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.
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