5G has given Beijing a development template to use across its Made in China 2025 program.
In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
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