Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
A report put together by Europe's HiPEAC high-performance computing research network argues computing is at an architectural turning point
SureCore is introducing an IP customization service intended to deliver SRAM cores tuned to specific power and performance requirements for wearable, wireless, augmented reality, and IoT devices.
ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.
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