Getting a RISC-V embedded toolchain in place
A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
design management
Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
Perforce buys Methodics
Version-control specialist Perforce Software has bought Methodics, which focuses on the lifecycle and traceability management of semiconductor IP.
Master the design and verification of next gen transport: Part Three – functional safety
The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Optimized DRC in the cloud
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Cadence presents plan for piecemeal cloud compute
Cadence has launched a web-based EDA service the company hopes will ease the transition from self-hosted computing to more flexible cloud-based development.
Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
FPGA playing verification catch-up as bugs escape
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Triage without tears: improving debug’s most human challenge
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.