Second formal check aids deadlock hunting
Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Author Archives: Paul Dempsey
Litho hotspot analysis gets machine-learning turbocharge
A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
FastSPICE upgrade boosts nano-scale analog verification by up to 10X
Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
Siemens raises Capital to full E/E design level
Capital has been grown from a wire harness suite to a full electrical/electronic platform with integration for digital twin strategies.
DVCon US 2020: Coronavirus program changes
DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.
DVCon US 2020 preview: ESD Alliance
The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.
Master the design and verification of next gen transport: Part Three – functional safety
The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
South Korea-Japan tensions continue to threaten memory supply chain
Concerns that the diplomatic stand-off between Seoul and Tokyo could hit the supply chain rose again this weekend as South Korean politicians made a surprise visit to disputed islands.
Roadmapping the quantum realm
The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.