Wilson Research Group

December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Article | Topics: Blog - EDA, - Market Research, Verification | Tags: bug, formal apps, formal verification, FPGA, programmable SoC, RISC-V, system-on-chip, SystemVerilog, VHDL | Organizations: Siemens, Siemens EDA, Wilson Research Group

November 27, 2020

RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

Article | Topics: Blog Topics, Blog - IP, - Market Research, Next Generation Design, Standards, Verification | Tags: automotive, CPU, mil/aero, MPU, RISC-V | Organizations: RISC-V International, Siemens, Siemens EDA, SiFive, Wilson Research Group

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