DATE: Dark clouds gather over 3D integration, panelist tells conference
The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.
Author Archives: Luke Collins
FD-SOI costs to match bulk by year end, says ST
STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.
Intel foundry to make Altera FPGAs
Intel's announcement that it will make FPGAs for Altera in an upcoming 14nm finFET process will reshape the programmable logic, and foundry, businesses.
Mentor updates HyperLynx for faster boards, more rules checking
Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
3D-IC integration prospects improving, say IEDM researchers
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
Process development needs hierarchy, abstraction, says tools CTO
How to save money in process development by moving experiments out of the fab and into the computer.
FD-SOI vs finFETs mulled during IEDM
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
Semiconductor roadmap gets fuzzier at IEDM
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
Ambipolar FETs are an each-way bet
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
Tile-based integration of analog functions enables power controller family
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi