FD-SOI costs to match bulk by year end, says ST

By Luke Collins |  No Comments  |  Posted: March 19, 2013
Topics/Categories: Blog Topics, Conferences  |  Tags: , , , , , ,  | Organizations: ,

The cost of producing chips on FD-SOI wafers (Guide) will match that of producing them on bulk by the end of the year, according to an ST representative speaking at the Design, Automation and Test Europe conference here in Grenoble today.

Philippe Magarshack, executive vice-president, design and enablement services for STMicroelectronics, told a special lunchtime session that the company is projecting that there will be little if any difference in cost between producing on SOI or bulk by year end. Although the wafers are 12 to 15% more expensive, the SOI lobby argues that the wafers are simpler to process because the channel is undoped, leading to a balancing cost saving.

Laurent Malier, director of CEA-Leti, the research organisation that has done a lot of work on SOI, added that there could be extra comparative savings as the two approaches move to denser process nodes, because some of the doping steps that are omitted in an FD-SOI process are on critical layers for which lithography is likely to  be complex and expensive.

Magarshack also rejected concerns about the supply of SOI wafers, saying his company is already qualifying two other suppliers – SEH and MEMC: “They are a few quarters behind in terms of qualifying so we are not worried about the supply of wafers. Supply will not be an issue.”

STMicroelectronics is continuing to promote FD-SOI processes, despite the unwinding earlier this week of the ST-Ericsson joint venture which provided ST’s flagship application for the process in the form of the NovaTHOR LTE modem chips.

“We remain fully committed to UTBB FD-SOI despite the ST-Ericsson announcement this week,” he said, adding that it is also continuing its product engineering work on novaTHOR, in the hope of finding other customers for it.

“We continue full speed on FD-SOI. We have many applications benefiting from FD-SOI other than the wireless space,” he added, mentioning design work on next-generation consumer products, and a high end networking application that could consume up to 300mm sq of silicon but has a power budget limited to 80W.

“We can save 30 to 40% of power with FD-SOI,” he said, adding that the company is also talking to potential customers about using the process in games consoles and digital still cameras.

Demonstrating further commitment, ST Microelectronics and CEA-Leti are also working on 14nm and 10nm variants of the process. Models are already available for the 14nm process, and a design kit is due in the third quarter. Models for the 10nm process are due early next year, with the design kit to follow.

Both nodes will involve further thinning the buried oxide layer in the SOI wafer, which makes applying a back bias voltage 60% more effective at controlling the transistors’ threshold voltage. For the 14nm process, ST will introduce in-situ doping of the raised source and drain, and will add germanium to the p-channel transistors to improve their performance. For the 10nm process, researchers are considering straining the thin silicon layer on top of the buried oxide to improve its carrier mobility.

Magarshack claimed that the 14nm process will be 40% faster than the 28nm process, and also benefit from the improved back bias control. Malier argued that the ability to apply varying amounts of back bias to different ‘islands’ of circuitry on the chip should be seen as a new systemic optimisation technique.

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