DAC2012: Can FD-SOI shrink chips, solve FinFET issue for SoCs?
What are the chances that FD SOI will become a mainstream process for future nodes?
Author Archives: Luke Collins
DAC2012: Blue Pearl partners Xilinx, develops grey-box approach to ARM cores
Blue Pearl is building alliances to bring its timing analysis tools to more users.
DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
DAC 2012: Atrenta to automate production of power-intent constraints
Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.
FinFET focus for June VLSI Symposia
Intel will reveal more details of its ‘Tri-Gate’ FinFET-based 22nm process at this year’s VLSI Symposium.
U2U links test and yield enhancement
Subtle data correlation and analysis techniques are helping to relate logic failures to particular types of manufacturing defect.
Technical Newsletter #3: Site updates, DATE highlights, CPTF, CDN
The headlines from DATE, CPTF and CDN Live. The latest technical articles. And new features. Our regular update.
Showtime! SNUG and U2U previews
We look at the upcoming Synopsys and Mentor Graphics user meetings in Santa Clara.
DATE notebook: Three ways to tackle design complexity
DATE panelists discuss three ways to tackle design complexity: by moving to higher levels of abstraction; by making more subtle use of existing synthesis strategies; and by better organisation.
DATE notebook: Collaboration key to advanced process nodes
Collaboration is becoming increasingly important to foundry companies as the development of advanced process nodes becomes more complex