Author Archives: Luke Collins

About Luke Collins

Luke Collins has spent 22 years covering electronics, EDA and innovation. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the international IP9x conference series on semiconductor IP. Luke's work has also appeared in The Economist, The Financial Times and Reseach-Technology Management.
June 5, 2013

FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
June 5, 2013

Jasper, Duolog bring formal verification to IP specification and assembly, low-power design

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: ,   |  Organizations: ,
June 3, 2013

CMOS “good for another century,” says father of finFET

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Article  |  Topics: Design to Silicon, Blog - IP  |  Tags: , , ,   |  Organizations:
May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , , , , , ,
May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 5, 2013

Synopsys users gather for European SNUG meetings

Synopsys users will be gathering at a series of SNUG meetings across Europe over the next month to share insights and experience of using Synopsys tools
Article  |  Topics: Conferences, Blog - EDA  |  Tags:   |  Organizations: , , , ,
May 5, 2013

IEDM2013 call for papers closing soon

It's time to act if you want your semiconductor device or process research to be considered for presentation at IEDM 2013 in Washington DC this December.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , ,   |  Organizations:
March 22, 2013

DATE: ARM proposes ‘unit of compute’ as basis for energy-efficient systems

ARM CPU chief proposes 'unit of compute' as building block for energy-efficient computation systems
Article  |  Topics: Conferences, Blog - Embedded  |  Tags: , , , , , , , , ,   |  Organizations:
March 20, 2013

DATE: Early shift to finFET processes challenges IP development strategies

An early shift to finFET processes is making developing IP libraries more challenging.
Article  |  Topics: Conferences, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: