The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.
Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Accellera Systems Initiative has created a working group to look at one of the knottiest problems in IC design: to simplify the job of checking designs when the bits come from so many sources and use languages that were not built for interoperability.
Cadence Design Systems has developed semiconductor IP for the automotive industry's OPEN Alliance to make ethernet the core networking backbone of future motor vehicles.
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