DVCon China 2019 preview: SmartDV

By TDF Staff |  No Comments  |  Posted: April 2, 2019
Topics/Categories: Blog - EDA, - Standards, Verification  |  Tags: , , , ,  | Organizations: ,

SmartDV will highlight its verification IP (VIP) for RISC-V applications at DVCon China (Booth #110). The conference and exhibition takes place April 17 at the Crowne Plaza Hotel in Century Park, Shanghai.

SmartDV’s TileLink VIP verifies the TileLink chip-scale interconnect fabric standard for RISC-V based SoCs to speed implementation and verification. It offers fast testbench development, and provides built-in coverage analysis. The VIP is fully compliant with the standard and runs on simulation environments from Synopsys, Cadence Design Systems and Mentor, as well as in the Metrics’ cloud-based simulation platform.

SmartDV’s Shanghai line-up will also include SimXL, its synthesizable transactors for Emulation and FPGA Prototyping. It is fully compliant with the major hardware-based verification platforms and also with standards specifications, including those for automotive, serial bus, memory, MIPI, networking, SoC interconnect fabrics, storage and video protocols.

Leave a Comment


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors