synthesis

Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.

Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.

Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.

Uses improved logic optimisations and a new approach to meeting timing.

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.