DAC 2022 preview: Breker Verification Systems
Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
synthesis
Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
DAC 2017 preview: Plunify
Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Real Intent tackles CDC at the physical level
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%
Uses improved logic optimisations and a new approach to meeting timing.
Xilinx revamps design software for new processes
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
DATE notebook: Constraints smooth path for FPGA synthesis
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
CDN Live: Cadence’s Encounter revamp collates innovation
Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.