DAC 2021 preview: SmartDV

By TDF Editor |  No Comments  |  Posted: December 3, 2021
Topics/Categories: Conferences, Digital/analog implementation, Blog - EDA, - RTL, Verification  |  Tags:  | Organizations: ,

Design and verification specialist SmartDV will highlight its extensive IP portfolio during the exhibition days at next week’s Design Automation Conference in San Francisco (Exhibition: Dec 6-8; Conference Dec 5-9)

Exhibiting at DAC 2021 Booth #2429 in Moscone West, the company will present IP compatible with all verification languages, platforms and methodologies.

SmartDV’s products can be found in markets that range across 5G, automotive, defense and aerospace, mobile, networking, SoC, serial bus, storage, and video and display markets and protocols.

SmartDV covers the design and verification flow from design through simulation, emulation, formal verification, post-silicon validation and memory modeling.

For markets such as these and others, the company’s Smart Compiler can be used to customize and create IP to customer specifications.

Email requests for demos or more information can be sent to demoATsmart-dvDOTcom or visit its staff at DAC 2021.

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