Breker Verification Systems will feature its advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration VIP in the TrekApps Family, as well as its popular SystemUVM Portable Stimulus class library and utilities at the Design Automation Conference (DAC) in San Francisco next week. It can be found at Booth #2528 of Moscone West during the DAC exhibition (July 11-13).
Breker’s will demo its System Coherency Synthesis TrekApp among other solutions, and its latest announcement will highlight an agreement the company has struck with RISC-V International (RVI).
Under the agreement, Breker will offer expertise in SoC verification solutions to RVI working groups.
As a strategic member of RVI, the company will influence the development of a cache coherency and integration test content platform for RISC-V processor development and end-use verification.
Breker’s test content synthesis leverages C++ and the Accellera Portable Stimulus Standard (PSS) specification models for UVM and SoC applications. The company offers a portfolio of TrekApps that generate high-coverage, optimized tests to address common verification scenarios, including cache coherency, security, power domain management, packet generation, and the integration of ARM and RISC-V processors.
The portfolio is already in use at many leading semiconductor companies.
DAC 2022 takes place at the Moscone West conference center in San Francisco. It is collocated with SEMICON West. The DAC conference runs July 10-14 and the exhibition from July 11-13.