Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Tenstorrent Ascalon processor core as part of the Imperas RISC-V model library.
Ascalon is a RISC-V processor that is designed to scale from edge to data center systems. The Imperas model matches Ascalon’s configuration space, including multicore and manycore options, with the aim of supporting fast simulations for software development and exploration of different system architectures.
“Any SoC developer that implements an IP processor core quickly discovers the fundamental interactions between the hardware and software design phases,” said Simon Davidmann, CEO at Imperas. “Now developers using the Ascalon IP can use the Imperas models as a reference for software development to support the shift-left of project schedules.”
The Imperas models of the Tenstorrent IP core portfolio are available now via www.OVPworld.org.
OVP models are typically published under the Apache 2.0 open-source license and include reference platforms, examples, and other collaborative projects from the community of OVP users.