Coverage features have been built into an increasing number of tools, but sometimes engineers need to go further to verify a design. Functional coverage is a good example because it depends on the intent underlying the particular project.
Mentor, a Siemens business, has now released a technical article that looks at templates and techniques that can be used to simply the creation of various coverage exercises.
The paper, ‘Covergate: Coverage exposed‘, is based on a paper that was originally presented at DVCon 2020, one of the many cornerstone events that suffered reduced attendance because of the Covid-19 pandemic.
Author Rich Edelman reviews the various strategies available and offers examples based on “techniques… with the simplest possible approach [which] will yield coverage reports that are easy to write, easy to debug and predictable.”
He maps out a vista that aims to demystify aspects of SystemVerilog and which also shows the important role played in achieving coverage goals by verification IP.
Edelman is offering the accompanying source code for his examples to readers.