RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose this week (December 13, 2022), Imperas Software has issued updates to its ImperasDV IP for RISC-V verification and Codasip has launched a secure-processor initiative based on the architecture following the acquisition of Cerberus Security Labs.
ImperasDV supports coverage-oriented verification in combination with SystemVerilog environments such as those offered by Cadence, Siemens EDA, and Synopsys. It goes beyond the basic instruction-set definitions on the basis that, as a processor has many complex states due to privilege modes, interrupts and dynamic effects, a coverage library needs to consider the complete operational behaviour of a processor, not just a block-level functional unit. The ImperasDV Verification IP options have been extended to include riscvISACOV, a set of SystemVerilog-source functional-coverage libraries for all of the ratified instruction extensions and the first release of the privilege mode libraries. Typically, these operations will be exercised in conjunction with controlled random generation of asynchronous events to ensure they work under all conditions.
“RISC-V offers new freedoms in design flexibility which is driving a new wave of innovation across the semiconductor industry in almost all market segments,” said Larry Lapides, vice president of sales at Imperas. “This is creating a resurgence in teams exploring custom processors with domain-specific optimized features, and as they take up the challenge of RISC-V processor verification, we are experiencing a massive shift in momentum as both new and established development teams invest massive amounts of time, energy and resources into processor verification.”
Codasip’s SecuRISC5 is an initiative to deliver reference designs that combine Codasip IP and third-party technology for secure processing platforms.
“Security is the ‘feature’ that people often fail to see the value in, but everyone knows they need. Another important aspect is that without security, there is no safety, and we are therefore adopting a holistic approach. We will help our customers integrate RISC-V safety and security by providing more than secure cores,” Jamie Broome, vice president of automotive and products at Codasip.
We will be working closely with Codasip anVijay Krishnan, General Manager, RISC-V Ventures at Intel, added, “e will be working closely with Codasip and other ecosystem partners to provide developers the opportunity to build and test out their secure concepts using Intel Pathfinder for RISC-V2 running in a trusted FPGA environment.”
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