October 18, 2012
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
October 17, 2012
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
October 16, 2012
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 15, 2012
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
October 11, 2012
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
October 11, 2012
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
October 11, 2012
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
October 9, 2012
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
October 9, 2012
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
October 8, 2012
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.