ST aims to seed more interest in FD-SOI
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
EDA
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
FinFETs face planar fightback at IEDM
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Intel, TSMC finFETs to star at IEDM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Is your 20nm process gate-last? Maybe it should be
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
TSMC updates reference flows for 20nm and CoWoS
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
Synopsys buys EVE and the death of dogma
The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
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