EDA

FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.

The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.

Cutting the cabling to simplify the emulation process.

SpringSoft is trying a different approach to constraint-based design in a bid to improve the automation of custom and mixed-signal design, particularly on advanced process nodes.

Mentor Graphics' CEO Wally Rhines picked out the trends he says can boost design productivity and drive growth for tools vendors at the company's Silicon Valley User2User conference

The specialist AMS foundry Triad Semiconductor has married its ViaASIC drag and drop libraries to Mentor Graphics' SystemVision design environment.

Companies need to collaborate with partners, vendors, and the rest of the supply chain if they are to achieve critical mass, Aart de Geus tells Synopsys user meeting.