Tech Design Forum
Briefing
gate-last
gate-last
October 11, 2012
Is your 20nm process gate-last? Maybe it should be
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
Article | Topics:
Blog - EDA
| Tags:
20nm
,
gate-first
,
gate-last
,
high-k metal gate (HKMG)
,
variability
| Organizations:
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