ST aims to seed more interest in FD-SOI

By Paul Dempsey |  No Comments  |  Posted: October 18, 2012
Topics/Categories: Blog Topics, Blog - EDA  |  Tags: , ,  | Organizations: ,

It’s not about volume, but today’s (October 18) deal on widening access to 28nm fully depleted silicon-on-insulator between STMicroelectronics, wafer manufacture Soitec and multi-project wafer (MPW) specialist Circuits Multi Projets (CMP) is worth noting.

It follows on from Spring’s FD-SOI (guide) 28nm and 20nm capacity deal with GlobalFoundries, which will see the foundry not only fab chips for ST and the 50/50 ST-Ericsson joint venture but also offer those first truly commercial flavors to other customers. This was a major boost for the technology’s ecosystem.

CMP’s additional role now is to keep the research flow going on multi-project wafers by releasing the 28nm technology to, primarily, universities and research organizations. For ST, after its development of and advocacy for FD-SOI, this provides a way of keeping it in mind while finFET and the latest 20nm CMOS processes have been stealing the headlines, and as the three competitors are commercialized. Think of it as a tap on the shoulder.

FD-SOI’s claims broad advantages over conventional bulk silicon on deep submicron processes for low-power circuits; and over finFETs because it includes the option to back-bias the channel and so gain greater control over the charge carriers flowing through it.

The MPWs are likely to be run through the FD-SOI line at ST’s smaller capacity Crolles fab, where much of the research into the technology has taken place.

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