EDA

Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.

MEMS relay-based devices offer the ultimate in subthreshold leakage: they don't have any. Design and technology advances are promising to overcome problems with reliability, design and speed, according to Tsu-Jae King Liu of UC Berkeley.

FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.

The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata