EDA

Cadence Design Systems has developed semiconductor IP for the automotive industry's OPEN Alliance to make ethernet the core networking backbone of future motor vehicles.

Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.

In a deal that pits the company head to head with ARM, Imagination Technologies has decided to buy the business of MIPS Technologies including the CPU architectures and cores. The price tag is $60m cash.

ARM is among the companies aiming to avoid a patent portfolio falling into the wrong hands after the break up of MIPS Technologies.

Altera has launched the first first SDK to take OpenCL software and target it to FPGAs rather than general-purpose processors or graphics processors.

ARM has named the first pair of processor cores that employ its 64bit architecture and revealed that an architectural clean-up is likely to result in the smaller of the pair requiring less silicon real estate than the existing 32bit Cortex-A9.

Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.