EDA

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.

The semiconductor industry is reaching a crunch point at which companies that form it have to work together much more closely, says Malcolm Penn of Future Horizons.

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.

The scope of the Low-Latency Interface (LLI) developed by the MIPI Alliance is expanding as it heads towards version 2 – increasing the ways in which a single DRAM array can be shared between SoCs in a mobile phone.

Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.

MEMS relay-based devices offer the ultimate in subthreshold leakage: they don't have any. Design and technology advances are promising to overcome problems with reliability, design and speed, according to Tsu-Jae King Liu of UC Berkeley.