EDA

GlobalFoundries and Samsung described how they are readying finFETs for production at CPTF 2013 and how the 28nm processes will have a long shelf life.

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.

Even though inventories are slack right, chipmakers could be struggling to find wafers in 2014.

Future Horizon’s forecast meeting for the first half of 2013 made it clear how the electronics sector and the semiconductor industry in particular is facing big problems.

14nm finFET test-chip designs are moving through Samsung's fab as ARM, Cadence Design Systems and Synopsys continue to check their flows on the new process.

In 2013, the Design Automation and Test in Europe (DATE) conference returns to Grenoble, France and with focus days on the Internet of Things and the cloud.

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs

Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.

The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.