Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
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