November 6, 2012

Companies go for patent protection in MIPS deal

ARM is among the companies aiming to avoid a patent portfolio falling into the wrong hands after the break up of MIPS Technologies.
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November 5, 2012

Altera embraces OpenCL with toolkit for FPGAs

Altera has launched the first first SDK to take OpenCL software and target it to FPGAs rather than general-purpose processors or graphics processors.
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October 30, 2012

ARM’s 64bit shift provides clean-up opportunity

ARM has named the first pair of processor cores that employ its 64bit architecture and revealed that an architectural clean-up is likely to result in the smaller of the pair requiring less silicon real estate than the existing 32bit Cortex-A9.
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October 30, 2012

Tektronix aims to slash FPGA prototype debug time

Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
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October 30, 2012

AMD mixes it up with ARM64 server processors

AMD adopts ARM64 to promote heterogeneous processing and encourage users to break with Intel and x86 in the enterprise market.
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October 30, 2012

ESL must go ‘pay to play’ for growth: Gary Smith

You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
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October 25, 2012

‘Known unknowns’ and the Cadence take on verification IP

Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
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October 25, 2012

Using verification IP to master AMBA and wider protocol proliferation

How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
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October 24, 2012

Tile-based integration of analog functions enables power controller family

Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
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