AMD mixes it up with ARM64 server processors
AMD adopts ARM64 to promote heterogeneous processing and encourage users to break with Intel and x86 in the enterprise market.
EDA
ESL must go ‘pay to play’ for growth: Gary Smith
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
Mentor Graphics CEO Wally Rhines – Interview
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
‘Known unknowns’ and the Cadence take on verification IP
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
Using verification IP to master AMBA and wider protocol proliferation
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Tile-based integration of analog functions enables power controller family
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
ST aims to seed more interest in FD-SOI
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
FinFETs face planar fightback at IEDM
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
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