EDA

October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm
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October 11, 2012

Is your 20nm process gate-last? Maybe it should be

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
October 9, 2012

TSMC updates reference flows for 20nm and CoWoS

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).


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October 9, 2012

Event alert: TSMC Open Innovation Platform

With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
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October 8, 2012

Synopsys buys EVE and the death of dogma

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
October 5, 2012

IEF: Process kits for processes that don’t yet exist

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.
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October 4, 2012

IEF: “Industry will have to cooperate”

The semiconductor industry is reaching a crunch point at which companies that form it have to work together much more closely, says Malcolm Penn of Future Horizons.
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October 4, 2012

IEF: Achronix plans embedded FPGA push

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.
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October 3, 2012

SAME: Memory-saving standard to expand

The scope of the Low-Latency Interface (LLI) developed by the MIPI Alliance is expanding as it heads towards version 2 – increasing the ways in which a single DRAM array can be shared between SoCs in a mobile phone.
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September 26, 2012

Cadence updates Allegro and Orcad

Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.

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