Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
EDA
Samsung moves further into 3D for denser flash
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec cuts transistor gap to less than 20nm with forksheets
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
AI’s design speedups, with and without machine learning
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
IEDM looks for papers across 2D devices to 3DICs
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Sigasi editor provided free for open-source hardware developers
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
Alternative scaling approaches form VLSI 2021 technology highlights
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
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