Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Mentor's Joe Sawicki talks to TDF about the growing importance of system-level simulation and the long-term impact of AI and cloud on EDA.
Moving design and verification activities into the cloud poses challenges. Next month's inaugural ES Design West will offer practical guidance.
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
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