EDA

Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.

Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.

The program for the 58th Design Automation Conference, which returns to a physical format in December, is online and is running its I Love DAC promotion for free access until the end of this month.

DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.

All engines in the place-and-route software have been boosted with cuts to runtime and memory footprint.

Packetized test and three new technologies provide the core of the company's DFT presentations during the virtual International Test Conference running this week.