EDA

Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.

IRPS will use a virtual format for its March conference and will take in the reliability of emerging as well as more established technologies.

Both Semicon West and DAC have been moved to December in anticipation of travel restrictions being much looser by then, with both events working on a hybrid physical and online format.

Pulsic has adopted the freemium approach with a tool that gives designers of analog circuits previews of how they will be implemented on-chip.

Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.

Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.

Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.