PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
EDA
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Sigasi editor provided free for open-source hardware developers
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
Alternative scaling approaches form VLSI 2021 technology highlights
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
US Republicans seek federal curbs on EDA sales to China
EDA's lower profile during the US-China semiconductor face-off could be coming to an end.
Siemens buys formal start-up OneSpin
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
Portable stimulus moves to version 2.0
The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
Navigating the Siemens EDA portfolio
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Accellera publishes security standard draft
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Cadence updates emulation and prototyping lineup
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.