May 2, 2021
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
April 16, 2021
EDA's lower profile during the US-China semiconductor face-off could be coming to an end.
April 16, 2021
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
April 15, 2021
The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
April 8, 2021
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
April 7, 2021
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
April 6, 2021
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
March 29, 2021
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
March 26, 2021
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
March 18, 2021
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.