EDA

May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
May 21, 2021

Cadence pushes its FastSpice to 32 cores

Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
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May 13, 2021

Sigasi editor provided free for open-source hardware developers

Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
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May 2, 2021

Alternative scaling approaches form VLSI 2021 technology highlights

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
April 16, 2021

US Republicans seek federal curbs on EDA sales to China

EDA's lower profile during the US-China semiconductor face-off could be coming to an end.
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
April 15, 2021

Portable stimulus moves to version 2.0

The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
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April 8, 2021

Navigating the Siemens EDA portfolio

The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
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April 7, 2021

Accellera publishes security standard draft

Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
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April 6, 2021

Cadence updates emulation and prototyping lineup

Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
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