Mentor is active across the program at Arm TechCon with a range of conference and booth talks, demonstrations and presentations.
Cadence has followed its launched of a parallelizable EM simulator with one that focuses on the thermal behavior of ICs through to multi-PCB assemblies.
DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
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