EDA

September 30, 2019

Arm TechCon 2019 preview: Mentor

Mentor is active across the program at Arm TechCon with a range of conference and booth talks, demonstrations and presentations.
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September 18, 2019

Cadence expands system analysis to thermal

Cadence has followed its launched of a parallelizable EM simulator with one that focuses on the thermal behavior of ICs through to multi-PCB assemblies.
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September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
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September 4, 2019

IEDM homes in on connected devices

The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
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September 3, 2019
Joe Sawicki, EVP for IC EDA, Mentor. 'AI inside' analysis

EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view

Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
August 23, 2019

Making the case for HLS in autonomous drive

The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
August 15, 2019

Optimized DRC in the cloud

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
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July 31, 2019

Accellera sets up public code repository

Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
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July 27, 2019

A repeatable methodology for modern reset domain crossing issues

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
July 11, 2019

C++ signoff made real

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
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