EDA

December 9, 2021

PDF and Siemens renew links for yield insights

Siemens has refreshed its collaboration with PDF Solutions with the aim of using test data and other sources to provide actionable information to improve device yield.
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December 6, 2021

Imperas pulls together tools for RISC-V verification

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
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December 6, 2021

DAC 2021 preview: Breker Verification Systems

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
December 3, 2021

Axiomise expands formal training services from beginner to expert

The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.
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December 3, 2021

DAC 2021 preview: SmartDV

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
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November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
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November 5, 2021

UK consortium starts work on cryogenic CMOS

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
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November 4, 2021

Design management survey points to more tactical cloud EDA

Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.
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November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.

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