Workshop sees the RISC-V ecosystem expand

By Chris Edwards |  No Comments  |  Posted: December 1, 2017
Topics/Categories: Blog - EDA, Embedded, IP  |  Tags: , , , , , ,  | Organizations: , , , ,

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.

Western Digital said it would use RISC-V cores to underpin its own designs that are intended to take advantage of the offloading of low-level data processing to storage subsystems. The company has taken an investment in RISC-V startup Esperanto Technologies as well as announcing plans to donate its own work on RISC-V to the open-source community.

Martin Fink, Western Digital CTO, said: “The open source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal. For that reason, we are providing all of our RISC-V logic work to the community.

“We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”

Microsemi’s own venture into the RISC-V ecosystem continued ahead of the workshop in the signing of a deal with UK-based debug specialist UltraSoC. Microsemi aims to use the UltraSoC debug IP in it forthcoming products based on the RISC-V instruction-set architecture (ISA). The move follows on from Microsemi’s adoption of the debug infrastructure in its disk-drive controllers.

Alan Nakamoto, Microsemi’s vice president of engineering services said: “We’re committed to providing a complete solution for development teams looking to leverage the RISC-V architecture, in a broad range of applications.”

UltraSoC also joined Andes Technology’s own efforts to build a tools ecosystem around its own IP processor cores based on RISC-V. Also in the partnership program are Imperas, Lauterbach, and Mentor, a Siemens business. Lauterbach has committed to offering debug support for the Andes cores and Mentor to supporting Andes’ RISC-V cores in the Veloce emulator. Andes said it has been providing updates for the Gnu and LLVM toolchains to support RISC-V cores.

At the workshop, Imperas unveiled its first set of fast processor models for RISC-V, with versions that support the 32bit N25 and 64bit X25 in the AndeStar V5 family, in addition to Microsemi FPGA and SiFive implementations. The processor models form part of a larger RISC-V Processor Developer Suite that includes standard software toolchains and a variety of profiling and performance and power-estimation tools.

Imperas has developed the models to be extensible in the expectation that SoC customers are likely to make modifications to processors to support specific applications.

Supported by a set of tools intended to accommodate customized processor cores, Czech-based Codasip said it has added a 64bit version of the RISC-V architecture to its existing line of 32bit cores, which scale down to a simple core with no pipeline.

“With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” said Karel Masařík, founder and CEO of Codasip. All of the cores are generated using the company’s Codasip Studio profiling and customization tool.

Aiming to expand the availability of RISC-V on a variety of processes, SiFive said it had joined GlobalFoundries’ FDXcelerator program, which is intended to build support for the foundry’s FD-SOI offering. SiFive aims to provide versions of the E31 and E51 processor cores that port readily to the 22FDX process.

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