Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.
Aimed at supporting the company’s own soft-core implementation of RISC-V developed to support its flash-based FPGAs, Ted Marena, director of product marketing at Microsemi, said the SoftConsole environment works for other versions of the core and that the company is keen to validate its tools against them in order to build up the RISC-V ecosystem.
Microsemi opted to support RISC-V as a more open alternative to the proprietary soft processor cores the company’s FPGA competitors currently promote. Marena said the introduction of the Windows-based IDE, supplementing an existing Linux toolchain, would help broaden the market for the open-source instruction set and the implementations that run it.
“A lot of initial interest was from Linux guys. But more and more people wanted Windows,” Marena said. “We wanted to step up and have the lead. We really think the key is that with its open-source nature, more people will use the core. And the more people who use the IDE, the more feedback we will have. The pace of innovation will speed up by having something like this in place.”
The company built 64bit support into the tool and has provided hooks to allow custom instruction extensions to be added. “To date there are no 64bit RISC-V cores available. But, down the road, we are looking to put 64bit cores into SoftConsole.”
Supporting Windows 7 and 10, the SoftConsole IDE is built on top of version 4.4 of the Eclipse framework and a number of the core plug-ins. The company is looking to port a number of RTOS implementations to its core, which uses a five-stage pipeline that can be instantiated with or without a cache. “Some customers don’t want to take up much room and don’t need the performance provided by a cache: they just want housekeeping functions for their design,” Marena said.