DVCon US 2017 preview: Mentor Graphics

By TDF Staff |  No Comments  |  Posted: February 15, 2017
Topics/Categories: Conferences, Blog - EDA, - Verification  |  Tags: , , , , ,  | Organizations: , , , , , , , ,

Verification conference DVCon US 2017 takes place from February 27 until March 2 at the Doubletree Hotel in San Jose. Mentor Graphics (Booth #1101) will be presenting demos, papers and tutorials around its Enterprise Verification Platform during the event.

A key session will run through the findings of the 2016 Trends in Functional Verification Study, a biennial project supported by Mentor and carried out independently by Collett International Research (February 28, 10:30am – 11:00am, Rm: Fir).

Mentor is also highlighting its participation in four tutorials during DVCon US 2017.

DVCon US 2017 tutorial highlights

Creating Portable Stimulus Models with the Upcoming Accellera Standard (February 27th, 9:00am – 12:00pm, Rm: Oak) sees the company join representatives from fellow EDA vendors Breker Verification Systems, Cadence Design Systems and Synopsys, as well as Analog Devices, Intel and Vayavya Labs. The session will preview the main features of the new standard for portable testbench components and provide some coding demonstrations of its capabilities.

SystemC Design and Verification – Solidifying the Abstraction Above RTL (February 27, 2:00pm – 5:00pm, Rm: Fir) features experts from Mentor, COSEDA Technologies, Intel and NXP Semiconductors in a review of progress in the development of the SystemC language and also the emerging UVM-SystemC standard, as well as a Q&A session.

Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify My Rescue Drone’s RTL? (March 2nd, 8:30am – 12:00pm, Rm: Siskiyou). In this tutorial, presenters from Mentor, Knowles and Microsemi will use the title challenge to explore the development and implementation of a full verification plan for a modern-day Robinson Crusoe.

Testbench Automation: How to Create a Complex Testbench in a Couple of Hours (March 2nd, 2:00pm – 5:30pm, Siskiyou) is a self-explanatory title for a pragmatic session. It will particularly concentrate on three new or recently introduced technologies that allow you to shrink testbench creation time: UVM Framework code generation; Verification IP configurators; and portable stimulus.

Mentor’s Dennis Brophy is chair for DVCon 2017 and offers his own broad-based overview of this year’s conference here.

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