Microsemi takes flash FPGAs to 28nm

By Chris Edwards |  No Comments  |  Posted: February 14, 2017
Topics/Categories: Blog - Embedded, PCB  |  Tags: , , ,  | Organizations:

Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices, armed with a flash technology licensed from Cypress Semiconductor.

The Polarfire family represents an attempt to capture a part of the market for communications-intensive designs from Altera and Xilinx by coupling relatively fast serial I/O with a programmable fabric that Microsemi claims offers lower cost at the system level than its competitors’ mid-range devices.

Ted Marena, director of FPGA product marketing at Microsemi, said the company is using UMC to fab the devices: “The 28nm process is lower cost than the high-k, metal gate and finFET processes of the competitors.”

Through the use of flip-chip packaging across the range together with the switching speed available on a 28nm process, the Polarfire devices support serdes speeds up to 12.7Gbit/s and local I/O at up to 1.6Gbit/s. The flip-chip packaging provides the ability to build devices with higher I/O counts than usual: the largest devices have up to 584 I/O pins. “We drove the packaging team to introduce this,” Marena said.

Following on from the company’s previous lines of non-volatile FPGAs, the company chose to move to Cypress’ SONOS flash technology to build the configuration cells. “It only needs a couple of additional layers compared to the base process,” Marena said, noting that the Microsemi team made tweaks to improve storage times.

Conventionally, SONOS memories tend to leak charge more than dedicated flash processes. The changes made by Microsemi extend the retention lifetime to 20 years for commercial and industrial temperature ranges, Marena said. The cells can be reprogrammed between 1000 and 10,000 times, he added.

A side-effect of the way in which the non-volatile cells have been added has been turned into a debug feature, Marena claimed. The Smart Debug matrix provides the ability to probe internal states while the device is running.

“It’s like having an oscilloscope but inside your chip. All of the other vendors let you recompile your design and implement the ability to probe. But we can take two points anywhere inside the silicon and bring them out to two pins. There is no recompiling required,” said Marena. “For customers this has saved weeks of debug time. You can also inject faults and errors into your design.”

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