Siemens EDA

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.

A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.

Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.

High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.

Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..