Siemens EDA

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

Mentor is packaging a range of software IP, reference designs, and technical help as VCO2S, for Vehicle Cockpit Consolidation Solutions.

Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.

The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.

Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.

Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.

Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.