The need to connect a growing range of devices to wireless networks is driving a trend to put RF circuitry onto SoCs built on advanced nodes. One of the key process technologies to support this is the ability to build capacitors that support the construction of cost-effective, fast, and accurate analog-digital converters.
In general, as engineers at Mentor, a Siemens business, explain in a recently published white paper, designers have access to two main forms of capacitor. One, usually provided by dedicated RF processes, is the metal-insulator-metal (MIM) technology. This uses additional process steps using two masks to build the parallel plates of the capacitors on top of the conventional metal stack. The metal-oxide-metal (MOM) type of integrated capacitor takes advantage of the metallization of the standard interconnect stack to create the passive devices. One example of the latter is the vertical natural capacitor (VNCap) or vertical parallel plate capacitor. Fingers built from multiple stacked metal layers that are connected using standard via create the target passive device.
As well as not requiring additional process steps, though it will consume the routing resource of an SoC, one key advantage of a VNCap-type MOM is that it can provide a higher capacitance per unit area. Its primary downside is that it will suffer from greater parasitic effects. Although MIM devices experience weaker parasitics, modelling of these effects is of prime importance in any SoC.
Because of the differences in construction, shape, and surrounding circuitry, parasitic extraction is a potentially complex exercise but a necessary endeavour. Though foundries with dedicated RF support and process design kits have pre-characterized parasitic models for a selected range of cells, simulated to a high degree of accuracy, there are layout-dependent effects that the models cannot capture even if the library contains examples that a designer can use.
Non-local effects, such as density, loading, thickness, and double-patterning mask shifts play major roles in determining the accuracy of a model on advanced nodes. The need to perform the assessment quickly but accurately calls for a technique that is faster than can be supported by a full-wave field solver but is more precise than a rules-based parasitic extraction tools.
The white paper explains how the Calibre xACT platform with Calibre xACT 3D and Calibre xL functionality fits into this role: providing post-layout simulation accurate enough for RF SoC requirements on advanced nodes. The Calibre xACT, xACT 3D, and xL tools all use TICER, a model order-reduction solution, to reduce parasitic netlist size without affecting the accuracy of the netlist, and to speed up downstream simulation and analysis.