Mentor automates silicon photonics layout
The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
Foundry
GlobalFoundries stops 7nm work to focus on existing processes
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
With RF, power and MRAM, FD-SOI finds its role
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Node-variant FinFET tweaks try to improve cost, performance
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
GlobalFoundries plays with metal gear in search for solid gains
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
DAC 2018 preview: Synopsys
DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
Motion harvester wins MEMS design contest
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
Layout schema generation speeds early-stage yield learning
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
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