Foundry

June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , ,
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
March 18, 2019

PCI may provide key to OCP chiplet standard

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
January 31, 2019

Creating a $4B market for silicon photonics

It's been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.
Article  |  Topics: Blog Topics  |  Tags: , , , ,   |  Organizations: , , , ,
December 12, 2018

IEDM shows progress on embedded eMRAM

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , , ,
November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations: , , , ,
October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,
September 12, 2018

Mentor automates silicon photonics layout

The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors