Foundry

February 6, 2013

GlobalFoundries inks IP deals

GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.
February 5, 2013

GlobalFoundries and Samsung talk finFET progress at CPTF

GlobalFoundries and Samsung described how they are readying finFETs for production at CPTF 2013 and how the 28nm processes will have a long shelf life.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
December 13, 2012

3D-IC integration prospects improving, say IEDM researchers

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
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December 11, 2012

FD-SOI vs finFETs mulled during IEDM

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
December 10, 2012

Germanium finFETs, TFETs and MEMS modelled at IEDM

The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
October 18, 2012

ST aims to seed more interest in FD-SOI

STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
Article  |  Topics: Blog Topics, Blog - EDA  |  Tags: , ,   |  Organizations: ,
October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
October 11, 2012

Intel, TSMC finFETs to star at IEDM

Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
Article  |  Topics: Blog Topics, Commentary, Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
October 9, 2012

TSMC updates reference flows for 20nm and CoWoS

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).


Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations:
October 9, 2012

Event alert: TSMC Open Innovation Platform

With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.

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