Foundry

Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound

Building the internet of Things will demand collaboration and a healthy ecosystem

Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling

Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.

STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.

Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.

Glass may be the high frequency interposer option given silicon concerns about power and noise. TSMC adds another pathfinder to its 3D arsenal.

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.